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www.powerint.com december 2010 LNK574 linkzero-lp zero no-load consumption integrated off-line switcher ? output power table product 4 230 vac 15% 85-265 vac adapter 2 open frame 3 adapter 2 open frame 3 LNK574dg 3 w 3 w 3 w 3 w table 1. output power table. notes: 1. iec 62301 clause 4.5 rounds standby power use below 5 mw to zero. 2. typical continuous power in a non-ventilated enclosed adapter measured at +50 c ambient. 3. maximum practical continuous power in an open frame design with adequate heatsinking, measured at 50 c ambient. 4. packages: d: so-8c. product highlights lowest system cost with zero no-load ? automatically enters zero input power mode when load is disconnected ? detects load reconnection and automatically restarts regulation ? simple upgrade to existing linkswitch-lp designs ? very tight ic parameter tolerances improve system manufactur - ing yield ? suitable for low-cost clampless designs ? frequency jittering greatly reduces emi flter cost ? extended package creepage improves system feld reliability advanced protection/safety features ? accurate hysteretic thermal shutdown protection C automatic recovery reduces feld returns ? universal input range allows worldwide operation ? auto-restart reduces delivered power by >85% during short- circuit and open loop fault conditions ? simple on/off control, no loop compensation needed ? high bandwidth provides excellent transient load response with no overshoot ecosmart ? C energy effcient ? no-load consumption as low as 4 mw at 230 vac input (note 1) ? easily meets all global energy effciency regulations with no added components ? on/off control provides constant effciency to very light loads applications ? chargers for cell/cordless phones, pdas, power tools, mp3/ portable audio devices, shavers, etc. description linkzero-lp is an upgrade to the popular linkswitch-lp, the industrys lowest component count charger/adapter and standby power switcher ic. the linkzero-lp controller incorporates new technology which enables the device to automatically enter into and wake up from no-load mode while taking less than 5 mw from the ac power. iec 62301 specifes measurements of standby power to a minimum accuracy of 10 mw, and so linkzero-lps consumption of substantially less than 5 mw at 230 vac rounds to zero based on the iec defnition. this low power level is also immeasurable on most power meters. the tightly specifed feedback (fb) pin voltage reference enables universal input primary side regulated power supplies with accurate constant voltage from 5% to full load. the start-up and operating power are derived directly from the drain pin which eliminates start-up circuitry. the internal oscillator frequency is jittered to signifcantly reduce both quasi-peak and average emi, minimizing flter cost. figure 1. typical application C not a simplifed circuit (a) and output characteristic envelope (b). (a) typical application schematic (b) output characteristic + d s fb bp/m dc output ac in linkzero-lp pi-5508-072610 i o i r v r v o rated output power = v r i r pi-5510-082310
rev. b 12/07/10 2 LNK574 www.powerint.com figure 2 functional block diagram. figure 3. pin confguration. pin functional description drain (d) pin: the power mosfet drain connection provides internal operating current for both startup and steady-state operation. bypass/multi-functional programmable (bp/m) pin: an external bypass capacitor for the internally generated 5.85 v supply is connected to this pin. the value of capacitor establishes the power down period. the minimum value of capacitor is 0.1 m f. an overvoltage protection disables the switching if the current into the pin exceeds 6.5 ma (i sd ). feedback (fb) pin: during normal operation, switching of the power mosfet is controlled by this pin. mosfet switching is disabled when a voltage greater than an internal v fb reference voltage is applied to the feedback pin. the v fb reference voltage is internally adjusted from 1.70 v at full load to 1.37 v at no-load in cv mode, and 1.70 v to 0.9 v in cc mode. below 0.9 v the part enters auto-restart operation. source (s) pin: this pin is the power mosfet source connection. it is also the ground reference for the bypass and feedback pins. pi-5507-060210 d package (so-8c) bp/m fb d 1 2 4 8 7 6 5 s s s s pi-5509-111810 clock oscillator 5.85 v 4.85 v 6.5 v 3 v pu overvoltage protection reset 0.9 v fault source (s) s r q dc max adj auto-restart counter reset jitter bypass/ multi function (bp/m) + - vi limit leading edge blanking + - drain (d) bypass pin undervoltage current limit feedback (fb) open loop pull up q + + + + regulator 5.85 v generator feedback ref 1.70 v - 1.37 v cc cut back 1.70 v - 0.9 v power down counter event counter system power down/ restart pu 160 f osc cycles
rev. b 12/07/10 3 LNK574 www.powerint.com linkzero-lp functional description linkzero-lp comprises a 700 v power mosfet switch with a power supply controller on the same die. unlike conventional pwm (pulse width modulation) controllers, it uses a simple on/ off control to regulate the output voltage. the controller consists of the following circuits, an oscillator, feedback (sense) 5.85 v regulator, bypass pin under/overvoltage protection, over-temperature protection, frequency jittering, current limit, leading edge blanking bypass pin clamp in power down and bypass mode. the controller includes a proprietary power down mode that automatically reduces standby consumption to levels that are immeasurable on most power meters. power down mode the device enters into power down mode (where mosfet switching is disabled) when the total load (power supply output plus bias winding loads) has reduced to ~0.6% of full load. the internal controller detects this condition by sensing when 160 cycles have been skipped twice with only one active switching cycle in between the two sets of 160 skipped switching cycles. during the power down period the bypass pin capacitor will discharge from 5.85 v down to about 3 v at which point the linkzero-lp will wake up and charge the bypass pin back up to 5.85 v. the wake up frequency is determined by the user through the choice of the bypass pin capacitor value (see figure 22 for bypass pin capacitor choice). once the bypass pin has recharged 5.85 v linkzero-lp senses if the load condition has changed or not, if not the linkzero-lp will enter into a new power down cycle or otherwise resumes normal operation (see applications example section for more details of power down mode operation). oscillator the typical oscillator frequency is internally set to an average of 100 khz. an internal circuit senses the on-time of the mosfet switch and adjusts the oscillator frequency so that at large duty cycle (low line voltage) the frequency is about 100 khz and at small duty cycle (high line voltage) the oscillator frequency is about 78 khz. this internal frequency adjustment is used to make the peak power point constant over line voltage. two signals are generated from the oscillator: the maximum duty cycle signal (dc max ) and the clock signal that indicates the beginning of a switching cycle. the oscillator incorporates circuitry that introduces a small amount of frequency jitter, typically 6% of the switching frequency, to minimize emi. the modulation rate of the frequency jitter is set to 1 khz to optimize emi reduction for both average and quasi-peak emissions. the frequency jitter, which is proportional to the oscillator frequency, should be measured with the oscilloscope triggered at the falling edge of the drain voltage waveform. the oscillator frequency is linearly reduced when the feedback pin voltage is lowered from 1.70 v down to 1.37 v. feedback input circuit cv mode the feedback input circuit reference is set at 1.70 v at full load and gradually reduces down to 1.37 v at no-load. when the feedback pin voltage reaches a v fb reference voltage (1.70 v to 1.37 v) depending on the load, a low logic level (disable) is generated at the output of the feedback circuit. this output is sampled at the beginning of each cycle. if high, the power mosfet is turned on for that cycle (enabled), otherwise the power mosfet remains off (disabled). since the sampling is done only at the beginning of each cycle, subsequent changes in the feedback pin voltage during the remainder of the cycle are ignored. feedback input cc mode when the feedback pin voltage at full load falls below 1.70 v, the oscillator frequency linearly reduces to typically 43% at the auto-restart threshold voltage of 0.9 v. this function limits the power supply output power at output voltages below the rated voltage regulation threshold v r (see figure 1). 5.85 v regulator the bypass pin voltage is regulated by drawing a current from the drain whenever the mosfet is off if needed to charge up the bypass pin to a typical voltage of 5.85 v. when the mosfet is on, linkzero-lp runs off of the energy stored in the bypass capacitor. extremely low power consumption of the internal circuitry allows linkzero-lp to operate continuously from the current drawn from the drain pin. a bypass capacitor value of 0.1 m f is suffcient for both high frequency decoupling and energy storage. 6.5 v shunt regulator and 8.5 v clamp in addition, there is a shunt regulator that helps maintain the bypass pin at 6.5 v when current is provided to the bypass pin externally. this facilitates powering the device externally through a resistor from the bias winding or power supply output in non-isolated designs, to decrease device dissipation and increase power supply effciency. the 6.5 v shunt regulator is only active in normal operation, and when in power down mode a clamp at a higher voltage (typical 8.5 v) will clamp the bypass pin. bypass pin undervoltage protection the bypass pin undervoltage circuitry disables the power mosfet when the bypass pin voltage drops below 4.85 v. once the bypass pin voltage drops below 4.85 v, it must rise back to 5.85 v to enable (turn on) the power mosfet. bypass pin overvoltage protection if the bypass pin gets pulled above 6.5 v (bp shunt )and the current into the shunt exceeds 6.5 ma a latch will be set and the power mosfet will stop switching. to reset the latch the bypass pin has to be pulled down to below 1.5 v. over-temperature protection the thermal shutdown circuit senses the die temperature. the threshold is set at 142 c typical with a 70 c hysteresis. when the die temperature rises above this threshold (142 c) the power mosfet is disabled and remains disabled until the die temperature falls by 70 c, at which point the mosfet is re-enabled. current limit the current limit circuit senses the current in the power mosfet. when this current exceeds the internal threshold (i limit ), the power mosfet is turned off for the remaining of that cycle. the leading edge blanking circuit inhibits the current limit
rev. b 12/07/10 4 LNK574 www.powerint.com comparator for a short time (t leb ) after the power mosfet is turned on. this leading edge blanking time has been set so that current spikes caused by capacitance and rectifer reverse recovery time will not cause premature termination of the mosfet conduction. auto-restart in the event of a fault condition such as output short-circuit, linkzero-lp enters into auto-restart operation. an internal counter clocked by the oscillator gets reset every time the feedback pin voltage exceeds the feedback pin auto- restart threshold voltage (v fb(ar) typical 0.9 v). if the feedback pin voltage drops below v fb(ar) for more than 145 ms to 170 ms depending on the line voltage, the power mosfet switching is disabled. the auto-restart alternately enables and disables the switching of the power mosfet at a duty cycle of typically 12% until the fault condition is removed. open loop condition on the feedback pin when an open loop condition on the feedback pin is detected, an internal pull up current source pulls the feedback pin up to above 1.70 v and linkzero-lp stops switching after 160 clock cycles. applications example the circuit shown in figure 4 is a typical isolated zero no-load 6 v, 350 ma, constant voltage, and constant current (cv/cc) output power supply using linkzero-lp. ac input differential fltering is accomplished by the flter formed by c1, c2 and l1. the proprietary frequency jitter feature of the linkzero-lp eliminates the need for any y capacitor or common- mode inductor. wire-wound resistor rf1 is a fusible, fame proof resistor which is used as a fuse as well as to limit inrush current. wire-wound types are recommended for designs that operate 132 vac to withstand the instantaneous power when ac is frst applied as c1 and c2 charge. the power supply utilizes simplifed bias winding voltage feedback, enabled by the linkzero-lp on/off control. the voltage across c5 is determined by the feedback pin reference voltage and the resistor divider formed by r3 and r4. capacitor c4 provides high frequency fltering on the feedback pin to avoid switching cycle pulse bunching. the feedback pin reference voltage, which varies with load, is set to 1.37 v at no-load and gradually increases to 1.70 v at full load to provide cable drop compensation. in the constant voltage (cv) region, the linkzero-lp device enables/disables switching cycles to maintain the feedback pin reference voltage. diode d6 and low cost ceramic capacitor c5 provide rectifcation and fltering of the primary feedback winding waveform. at increased loads, beyond the maximum power threshold, the ic transitions into the constant current (cc) region. in this region, the feedback pin voltage begins to reduce as the power supply output voltage falls. in order to maintain a constant output current, the internal oscillator frequency is reduced in this region until it reaches typically 48% of the starting frequency. when the feedback pin voltage drops below the auto-restart threshold (typically 0.9 v on the feedback pin), the power supply enters the auto-restart mode. in this mode, the power supply will turn off for 1.2 s and then turn back on for 170 ms. the auto-restart function reduces the average output current during an output short-circuit condition. the linkzero-lp device is self biased through the drain pin. however, to improve effciency at high line, an external bias may be added using optional components diode d5 and resistor r2. the power down (pd) mode duty cycle and the no-load power figure 4. schematic of 2.1 w, 6 v, 350 ma, 0.00 w adapter/charger. pi-6086-072110 d s fb bp/m r1 4.7 k r3 113 k 1% r2 82 k r5 5.1 r4 9.09 k 1% rf1 10 2 w d7 ss15 d5 1n4148 d6 dl4003 d1 1n4007 d2 1n4007 d3 1n4007 d4 1n4007 t1 ef16 5 nc 9 8 2 1 4 c7 330 f 16 v c4 1 nf 50 v c5 220 nf 50 v c6 220 pf 100 v c3 220 nf 50 v l1 1.0 mh 6 v, 350 ma rtn u1 LNK574dg linkzero-lp 85 - 265 vac c1 3.3 f 400 v c2 3.3 f 400 v
rev. b 12/07/10 5 LNK574 www.powerint.com consumption is determined by the bypass pin capacitor c3. no-load power consumption can be reduced by a capacitor with higher value. higher c3 capacitor values will tend to increase the output ripple in pd mode - see linkzero-lp design considerations section below. a clampless primary circuit is achieved due to the very tight tolerance current limit trimming techniques used in manufacturing the linkzero-lp, plus the transformer construction techniques used. the peak drain voltage is therefore limited to typically less than 550 v at 265 vac, providing signifcant margin to the 700 v minimum drain voltage specifcation (bv dss ). output rectifcation and fltering is achieved with output rectifer d7 and flter capacitor c7. due to the auto-restart feature, the average short circuit output current is signifcantly less than 1 a, allowing low current rating and low cost rectifer d7 to be used. output circuitry is designed to handle a continuous short circuit on the power supply output. although not necessary in this design, a preload resistor may be used at the output of the supply to reduce output voltage at no-load. linkzero-lp power down (pd) mode design considerations the linkzero-lp goes into pd mode when the output power supply load is reduced enough that 160 consecutive switching cycles are skipped twice with only one active switching cycle in between the two sets of 160 skipped switching cycles. this corresponds to ~0.6% of the full load power capability of the linkzero-lp. even when the power supply output load is completely removed, any preload resistor on the output and the components connected to the bias winding still represent a load on the transformer. the feedback circuitry connected to the bias winding should therefore be designed to represent <0.6% of the power supply full load. otherwise linkzero-lp will not be able to detect a no-load condition on the output and will not enter pd mode thereby disabling the beneft of zero no-load input power. in the case of the design of figure 4, the power supply full load output power is 2.1 w (6 v, 350 ma). the bias winding load should therefore be designed to be <<0.6% of this (<12.6 mw). in the example of figure 4, the average no-load voltage across bias winding capacitor c5 is approximately 20 v. the loading of r3, r4 and r2 (if used) should therefore be chosen to present <12.6 mw load with this bias voltage. in the case shown, the r2 path consumes ~3.3 mw and r3 and r4 also consumes ~3.3 mw. so the total consumption of 6.6 mw meets the criteria necessary to ensure the power supply will enter pd mode when the power supply load is removed. adjusting the power consumption of the circuitry connected to the bias winding can therefore be used to adjust the power supply output power threshold at which the linkzero-lp goes into pd mode. it can be seen therefore that, if desired, pd mode can be avoided altogether simply by adding a preload resistor on the output of the power supply or increasing the load on the bias winding to >0.6% (plus margin) of the power supply maximum power capability. when the linkzero-lp is in pd mode, the time taken for the bypass pin voltage to discharge to v bppdreset (~3 v) determines the duration of the pd off-time. the duration of the pd off time also determines the ripple on the output voltage. if components d5 and r2 are not used in figure 4, this time is determined purely by the choice of c3. if however d5 and r2 are used to provide an external bypass pin supply, then a combination of the energy stored in c5 and c3 determine the pd off time before the bypass pin voltage reaches the v bp(pu) (~3 v). in either case, c5 is completely discharged through r3 and r4 during the pd off time (d5 prevents the bypass capacitor c3 being discharged through this path). c5 is therefore kept as small as possible to reduce the power supply no-load input power consumption associated with recharging this capacitor at the start of the next pd on time. the minimum value of c5 is determined by the time constant set up with the feedback resistors r3 and r4 to avoid excessive cycle by cycle ripple on c5 infuencing the output voltage regulation. the typical choice for c5 is between 100 nf and 330 nf. when d5 and r2 are used, the minimum value of bias winding capacitor c5 is again governed by voltage regulation performance so the value of bypass pin capacitor c3 is typically reduced to reduce pd off time period if required. a minimum c3 value of 47 nf is recommended. pcb layout considerations linkzero-lp layout considerations layout see figure 5 for a recommended circuit board layout for linkzero-lp (u1). single point grounding use a single point ground (kelvin) connection from the input flter capacitor to the area of copper connected to the source pins. bypass capacitor (c bp ), feedback pin noise filter capacitor (c fb ) and feedback resistors to minimize loop area, these two capacitors should be physically located as near as possible to the bypass and source pins, and feedback pin and source pins respectively. also note that to minimize noise pickup, feedback resistors r fb1 and r fb2 are placed close to the feedback pin. primary loop area the area of the primary loop that connects the input flter capacitor, transformer primary and linkzero-lp should be kept as small as possible. primary clamp circuit an external clamp may be used to limit peak voltage on the drain pin at turn off. this can be achieved by using an rcd clamp or a zener (~200 v) and diode clamp across the primary winding. in all cases, to minimize emi, care should be taken to minimize the circuit path from the clamp components to the transformer and linkzero-lp (u1).
rev. b 12/07/10 6 LNK574 www.powerint.com thermal considerations the copper area underneath the linkzero-lp (u1) acts not only as a single point ground, but also as a heatsink. as it is connected to the quiet source node, this area should be maximized for good heat sinking of u1. the same applies to the cathode of the output diode. y capacitor the placement of the y-type capacitor (if used) should be directly from the primary input flter capacitor positive terminal to the common/return terminal of the transformer secondary. such a placement will route high magnitude common-mode surge currents away from u1. note: if an input emi flter is used, the inductor in the flter should be placed between the negative terminals on the input flter capacitors. output diode (d o ) for best performance, the area of the loop connecting the secondary winding, the output diode (d o ) and the output flter capacitor (c o )should be minimized. in addition, suffcient copper area should be provided at the anode and cathode terminals of the diode for heat sinking. a larger area is preferred at the electrically quiet cathode terminal. a large anode area can increase high frequency conducted and radiated emi. resistor r s and c s represent the secondary side rc snubber. quick design checklist as with any power supply design, all linkzero-lp designs should be verifed on the bench to make sure that component specifcations are not exceeded under worst-case conditions. figure 5. pcb layout of a 2.1 w, 6 v, 350 ma charger. + C hv dc in + C lv dc out transformer c b r fb1 t1 j3 r6 c o d o u1 c fb r fb2 d bp r bp c bp d b r s c s pi-6098-092410 the following minimum set of tests is strongly recommended: 1. maximum drain voltage C verify that v ds does not exceed 660 v at the highest input voltage and peak (overload) output power. this margin to the 700 v bv dss specifcation gives margin for design variation, especially in clampless designs. 2. maximum drain current C at maximum ambient temperature, maximum input voltage and peak output (overload) power, verify drain current waveforms for any signs of transformer saturation and excessive leading-edge current spikes at startup. repeat under steady state conditions and verify that the leading-edge current spike event is below i limit(min) at the end of the t leb(min) . under all conditions, the maximum drain current should be below the specifed absolute maximum ratings. 3. thermal check C at specifed maximum output power, minimum input voltage and maximum ambient temperature, verify that the temperature specifcations are not exceeded for linkzero-lp, transformer, output diode and output capacitors. enough thermal margin should be allowed for part-to-part variation of the r ds(on) of linkzero-lp as speci - fed in the data sheet. under low line and maximum power, maximum linkzero-lp source pin temperature of 100 c is recommended to allow for these variations. 4. negative drain voltages C clampless designs may allow the drain voltage to ring below source and cause reverse currents to fow from source to drain. verify that any such current remains within the envelope shown in figure 9.
rev. b 12/07/10 7 LNK574 www.powerint.com parameter symbol conditions source = 0 v; t j = -40 to 125 c (unless otherwise specifed) min typ max units control functions output frequency f osc t j = 25 c v fb = 1.70 v, see note c 93 100 107 khz frequency jitter peak-peak jitter compared to average frequency, t j = 25 c 3 % ratio of output frequency at auto-restart to f osc f osc(ar) f osc t j = 25 c v fb = v fb(ar) see note b 43 % maximum duty cycle dc max 60 63 % feedback pin voltage at no skipped cycles v fb 1.63 1.70 1.77 v feedback pin voltage at 99.4% skipped cycles v fb(nl) 1.37 v feedback pin voltage at auto- restart v fb(ar) 0.8 0.9 1.05 v absolute maximum ratings (1,6) drain voltage .................................. ......... ..............-0.3 v to 700 v peak drain current LNK574 .............................. 200 (375) ma (2) peak negative pulsed drain current ................... ......... -100 ma (3) feedback voltage ................................................. ....... -0.3 v to 9 v feedback current ................................................. .............. 100 ma bypass pin voltage ...................................... ............. -0.3 v to 9 v bypass pin voltage in power down mode ........ -0.3 v to 11 v (7) storage temperature ...................................... ..... -65 c to 150 c operating junction temperature................. .... -40 c to 150 c (4) lead temperature ....................................................... ........ 260 c (5) notes: 1. all voltages referenced to source, t a = 25 c. 2. higher peak drain current allowed while drain source voltage does not exceed 400 v. 3. duration not to exceed 2 m s. 4. normally limited by internal circuitry. 5. 1/16 in. from case for 5 seconds. 6. maximum ratings specifed may be applied, one at a time without causing permanent damage to the product. exposure to absolute maximum ratings for extended periods of time may affect product reliability. 7. maximum current into pin is 300 m a. thermal resistance thermal resistance: d package: ( q ja ) .......................... ........ 100 c/w (2) ; 80 c/w (3) ( q jc ) .................................................. ....... 30 c/w (1) notes: 1. measured on the source pin close to plastic interface. 2. soldered to 0.36 sq. in. (232 mm 2 ), 2 oz. copper clad. 3. soldered to 1 sq. in. (645 mm 2 ), 2 oz. copper clad.
rev. b 12/07/10 8 LNK574 www.powerint.com parameter symbol conditions source = 0 v; t j = -40 to 125 c (unless otherwise specifed) min typ max units control functions (cont.) minimum switch on-time t on(min) 700 ns drain supply current i s1 feedback voltage > v fb (mosfet not switching) 150 200 260 m a i s2 0.9 v v fb 1.70 v (mosfet switching) 200 250 310 bypass pin charge current i ch1 v bp = 0 v, t j = 25 c -5.5 -3.8 -1.8 ma i ch2 v bp = 4 v, t j = 25 c -3.8 -2.5 -1.0 bypass pin voltage v bp 5.60 5.85 6.10 v bypass pin voltage hysteresis v bp(h) 0.8 1.0 1.2 v bypass pin shunt voltage bp shunt 6.1 6.5 6.9 v circuit protection current limit i limit di/dt = 40 ma/ m s t j = 25 c 126 136 146 ma power coeffcient i 2 f di/dt = 40 ma/ m s t j = 25 c 1665 1850 2091 a 2 hz leading edge blanking time t leb t j = 25 c 220 265 ns bypass pin shutdown threshold current i sd v bp = bp shunt see note e 5.0 6.5 8.0 ma thermal shutdown temperature t sd see note b 135 142 150 c thermal shutdown hysteresis t sd(h) see note b 70 c power down (pd) mode off-state drain leakage in power down mode i dss(pd) t j = 25 c, v drain = 325 v see figure 23 6.5 9 m a bypass pin overvoltage protection in power down mode v bp(pdp) i bp = 300 m a t j 100 c 7.25 8.5 10.9 v bypass pin power up reset threshold (in power down mode or at power supply start-up) v bp(pu) 1.5 3 4 v
rev. b 12/07/10 9 LNK574 www.powerint.com parameter symbol conditions source = 0 v; t j = -40 to 125 c (unless otherwise specifed) min typ max units output on-state resistance r ds(on) i d = 13 ma t j = 25 c 48 55 w t j = 100 c 76 88 breakdown voltage bv dss v bp = 6.2 v, t j = 25 c 700 v drain supply voltage 50 v auto-restart on-time t ar v in = 85 vac, t j = 25 c, see note d 145 ms auto-restart off-time 1.0 s output enable delay t en see figure 8 14 m s notes: a. i dss is the worse case off state leakage specifcation at 80% of bv dss and maximum operating junction temperature. b. this parameter is derived from characterization. c. output frequency specifcation applies to low line input voltage in the fnal application. the controller is designed to reduce output frequency by approximately 20% at high line input voltages to balance low line and high line maximum output power. d. the auto-restart on-time/off-time is increased by 20% at high line input 265 vac. e. linkzero-lp shuts down if current into bypass pin reaches i sd at bp shunt voltage.
rev. b 12/07/10 10 LNK574 www.powerint.com figure 7. duty cycle measurement. figure 8. output enable timing. figure 6. general test circuit. figure 9. peak negative pulsed drain current waveform. pi-3707-112503 fb t p t en dc max t p = 1 f osc v drain (internal signal) 0 100 t ime (ms) drain current (ma) pi-4021-101305 -100 2 ms s s s s bp/m fb d pi-6067-072110 470 5 w s1 50 v 0-2 v 0.1 f
rev. b 12/07/10 11 LNK574 www.powerint.com typical performance characteristics 1.1 1.0 0.9 -50 -25 0 2 5 5 0 7 5 100 125 150 junction temperature (c) breakdown voltage (normalized to 25 c) pi-2213-012301 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 junction temperature ( c) pi-6065-071910 output frequency (normalized to 25 c) 1.4 1.0 1.2 0.8 0.6 0.4 0.2 0 -50 0 50 100 150 temperature ( c) pi-6066-071910 current limit (normalized to 25 c) 1.1 1.0 0.9 -50 -25 0 2 5 5 0 7 5 100 125 150 t emperature (c) feedback pin v oltage (normalized to 25 c) pi-4057-071905 6 5 4 3 2 1 0 0 0.2 0.4 0.6 0.8 1.0 t ime (ms) pi-2240-012301 byp ass pin v oltage (v) 7 100 150 175 200 125 0 0 4 2 8 6 1 0 1 2 1 4 1 6 1 8 2 0 drain v oltage (v) drain current (ma) pi-3927-083104 25 75 50 25 0c 100 0c c248?6444 ?20- 4??641220c26 4 c248?6444 c2 4?4??641220c26 c248?6444 ??
4 40?c4?0?2?4 ? 4?4?6??4 1 6 c24886444 2?c2 4??641220c26 c248?6444 ????
?4 4?70 24??641220c26 c248?6444 cc4?002??64
rev. b 12/07/10 12 LNK574 www.powerint.com drain v oltage (v) drain capacitance (pf) pi-3928-083104 0 100 200 300 400 500 600 1 10 100 1000 typical performance characteristics (cont.) figure 16. c dss vs. drain voltage. figure 18. feedback pin regulation voltage threshold vs. output load in cv mode. figure 20. feedback pin input characteristics in cc mode (1.7 v to 0.9 v). figure 17. frequency reduction vs. duty cycle (line voltage). figure 19. feedback pin input characteristics. figure 21. frequency cut back in cc mode normalized to 1. 110 100 90 80 70 60 0 10 20 30 40 50 60 70 duty cycle (%) pi-6068-071910 frequency (khz) 1.8 1.7 1.6 1.5 1.4 1.3 0 10 20 30 40 50 60 70 80 90 100 output load (%) pi-6069-072110 feedback pin voltage (v) 50 40 30 20 0 10 -10 -20 -30 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 feedback pin voltage (v) pi-6070-072110 feedback pin current (a) 0 -4 -2 -6 -8 -10 -12 -14 -16 -18 -20 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 feedback pin voltage (v) pi-6071-072110 feedback pin current (a) 0 -3 -2 -1 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 frequency normalized to 1 pi-6072-072110 feedback pin current (a) auto-restart
rev. b 12/07/10 13 LNK574 www.powerint.com typical performance characteristics (cont.) figure 22. power down off-time vs. bypass pin capacitor. v bp start at 5.85 v (temperature = 25 c) figure 23. typical drain current vs. temperature in power down mode. 1 0.8 0.9 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 200 400 600 800 1000 1200 1400 power down off-time (ms) pi-6110-112310 bypass pin capacitor ( f) 10 9 8 7 6 5 4 3 2 1 0 -50 -25 0 25 50 75 100 125 temperature (c) pi-6111-081810 drain current (a)
rev. b 12/07/10 14 LNK574 www.powerint.com pi-4526-0401 10 d07c so-8c (d package) 3.90 (0.154) bsc notes: 1. jedec reference: ms-012. 2. package outline exclusive of mold flash and metal burr . 3. package outline inclusive of plating thickness. 4. datums a and b to be determined at datum plane h. 5. controlling dimensions are in millimeters. inch dimensions are shown in parenthesis. angles in degrees. 0.20 (0.008) c 2x 1 4 5 8 2 6.00 (0.236) bsc d 4 a 4.90 (0.193) bsc 2 0.10 (0.004) c 2x d 0.10 (0.004) c 2x a-b 1.27 (0.050) bsc 7x 0.31 - 0.51 (0.012 - 0.020) 0.25 (0.010) m c a-b d 0.25 (0.010) 0.10 (0.004) (0.049 - 0.065) 1.25 - 1.65 1.75 (0.069) 1.35 (0.053) 0.10 (0.004) c 7x c h o 1.27 (0.050) 0.40 (0.016) gauge plane 0 - 8 1.04 (0.041) ref 0.25 (0.010) bsc sea ting plane 0.25 (0.010) 0.17 (0.007) det ail a det ail a c sea ting plane pin 1 id b 4 + + + 4.90 (0.193) 1.27 (0.050) 0.60 (0.024) 2.00 (0.079) reference solder pad dimensions + part ordering information ? linkzero product family ? linkzero-lp series number ? package identifer d plastic so-8c ? package material g green: halogen free and rohs compliant ? tape & reel and other options blank standard confgurations tl tape & reel, 2.5 k pcs minimum for d package. not available for p package. lnk 574 d g - tl
rev. b 12/07/10 15 LNK574 www.powerint.com notes
for the latest updates, visit our website: www.powerint.com power integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. power integrations does not assume any liability arising from the use of any device or circuit described herein. power integrations makes no warranty herein and specifically disclaims all warranties including, without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement of third party rights. patent information the products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one or more u.s. and foreign patents, or potentially by pending u.s. and foreign patent applications assigned to power integrations. a complete list of power integrations patents may be found at www.powerint.com. power integrations grants its customers a license under certain patent rights as set forth at http://www.powerint.com/ip.htm. life support policy power integrations products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of power integrations. as used herein: 1. a life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in signifcant injury or death to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. the pi logo, topswitch, tinyswitch, linkswitch, dpa-switch, peakswitch, cpazero, senzero, ecosmart, clampless, e-shield, filterfuse, stakfet, pi expert and pi facts are trademarks of power integrations, inc. other trademarks are property of their respective companies. ?2010, power integrations, inc. power integrations worldwide sales support locations world headquarters 5245 hellyer avenue san jose, ca 95138, usa. main: +1-408-414-9200 customer service: phone: +1-408-414-9665 fax: +1-408-414-9765 e-mail: usasales@powerint.com china (shanghai) room 1601/1610, tower 1 kerry everbright city no. 218 tianmu road west shanghai, p.r.c. 200070 phone: +86-21-6354-6323 fax: +86-21-6354-6325 e-mail: chinasales@powerint.com china (shenzhen) rm a, b & c 4th floor, block c, electronics science and technology bldg., 2070 shennan zhong rd, shenzhen, guangdong, china, 518031 phone: +86-755-8379-3243 fax: +86-755-8379-5828 e-mail: chinasales@powerint.com germany rueckertstrasse 3 d-80336, munich germany phone: +49-89-5527-3910 fax: +49-89-5527-3920 e-mail: eurosales@powerint.com india #1, 14th main road vasanthanagar bangalore-560052 india phone: +91-80-4113-8020 fax: +91-80-4113-8023 e-mail: indiasales@powerint.com italy via de amicis 2 20091 bresso mi italy phone: +39-028-928-6000 fax: +39-028-928-6009 e-mail: eurosales@powerint.com japan kosei dai-3 bldg. 2-12-11, shin-yokohama, kohoku-ku yokohama-shi kanagwan 222-0033 japan phone: +81-45-471-1021 fax: +81-45-471-3717 e-mail: japansales@powerint.com korea rm 602, 6fl korea city air terminal b/d, 159-6 samsung-dong, kangnam-gu, seoul, 135-728, korea phone: +82-2-2016-6610 fax: +82-2-2016-6630 e-mail: koreasales@powerint.com singapore 51 newton road #15-08/10 goldhill plaza singapore, 308900 phone: +65-6358-2160 fax: +65-6358-2015 e-mail: singaporesales@powerint.com taiwan 5f, no. 318, nei hu rd., sec. 1 nei hu dist. taipei, taiwan 114, r.o.c. phone: +886-2-2659-4570 fax: +886-2-2659-4550 e-mail: taiwansales@powerint.com europe hq 1st floor, st. jamess house east street, farnham surrey gu9 7tj united kingdom phone: +44 (0) 1252-730-141 fax: +44 (0) 1252-727-689 e-mail: eurosales@powerint.com applications hotline world wide +1-408-414-9660 applications fax world wide +1-408-414-9760 revision notes date a internal release. 10/12/10 b updated text and parameter tables. 12/07/10

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